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08:00:00","2026-10-19 08:00:00","public","2026-10-12 08:00:00",{"id":63,"slug":64,"title":65,"logo":66,"publicLiveEmbedUrl":7,"description":67,"introduction":57,"organizer":18,"coOrganizer":5,"sponsor":68,"startTime":69,"endTime":70,"status":33,"dashboardVisibility":23,"createdAt":71,"updatedAt":72},"019af3f3-e06a-7245-aa8d-37dc99a69c73","winter2025","2025年冬季InfiniTensor大模型与人工智能系统训练营","https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fuploads\u002F2025-12\u002F019afc69-b7ca-7805-91fb-605429671c01.png?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=E67XHLL7db9GOlGHdVrBAdjqtXU%3D","由启元实验室发起的InfiniTensor大模型与人工智能系统训练营，面向开源社区、高校及产业界伙伴开放。活动以「普及AI全栈知识技术、培养工程实践与创新型人才、推广国产软硬件技术生态」为核心目标，助力国家人工智能产业高质量发展。 \n","新华三技术有限公司","2025-12-25 08:00:00","2026-03-27 08:00:00","2025-12-06 08:00:00","2026-10-22 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20:24:49",[44],{"currentItem":105,"processedData":125},{"img":106,"keywords":107,"treeType":44,"description":108,"showStatus":44,"updateTime":109,"type":110,"title":111,"content":112,"nextArticle":113,"createTime":109,"sortOrder":117,"canonicalPath":118,"id":119,"contentType":120,"prevArticle":121},"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_fm.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=NNBCWO6xMS6WhvaDeCmIRTXfWlI%3D","InfiniTensor,冬季训练营,AI编译器,MLIR,AscendNPU IR","解析 MLIR 与 AscendNPU IR 编译堆栈，梳理 AI 编译器流程与后端优化思路。","2026-10-22 20:38:11",2,"InfiniTensor 冬季训练营 AI 编译器第七课《(MLIR)AscendNPU IR 编译堆栈》","![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw01.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=scKa%2BKANnxa0JRQqbi7iGpM%2BPzo%3D)\r\n\r\n\r\n2026 年 1 月 28 日，2025 冬季 InfiniTensor 大模型与人工智能系统训练营 AI 编译器系列第七课《(MLIR)AscendNPU IR 编译堆栈》开讲。\r\n\r\n本节课主要讲解 AscendNPU IR 架构。\r\n\r\n## AscendNPU IR 架构概述\r\n### Triton-Ascend + AscendNPU IR\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw02.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=IU0h3kblaeY3ocmOSmY3Y6fseAg%3D)\r\n\r\n### MLIR 简介：\r\n#### 1. 定义：\r\n- MLIR（Multi-Level Intermediate Representation）是一种开源的编译基础设施，旨在通过统一且可扩展的中间表示解决软件碎片化和编译效率问题。\r\n#### 2. 特点：\r\n- 多层方言（Dialects）支持，从高层计算图到低层硬件指令的全栈抽象。\r\n\r\n### AscendNPU IR 引入：\r\n- 背景：为了支持更多前端编程语言和硬件平台，特别是在NPU（如昇腾NPU）上的优化。\r\n- 目标：通过 AscendNPU IR 实现高效编译和硬件优化。\r\n\r\n## AscendNPU IR 架构详解\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw03.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=qOhMVKHpuehK4S80l37YCBxhjqY%3D)\r\n\r\n### 整体架构：\r\n#### 1. 方言层级：\r\n- AscendNPU IR 采用多层方言设计，主要包括 Hfusion 和 HIVM 两层核心方言，辅以Annotation、HACC、Scope等辅助方言。\r\n\r\n#### 2. 转换流程：\r\n- 从前端 DSL 到 Triton IR，再到 TritonGPU IR（或 MLIR 公共方言如 Linalg），最终转换为AscendNPU IR，并编译成二进制文件。\r\n\r\n#### 3. 核心方言解析：\r\n- **Hfusion：**\r\n  - **设计原理：** 基于 Linalg 的扩展，采用命名 OP 保留高层语义信息。\r\n  - **功能：** 数据预处理、OP 简化、类型转换等，不直接涉及硬件细节。\r\n  - **优化：** 合法性检查、冗余操作消除、高层 OP 分解等。\r\n- **HIVM：**\r\n  - **设计原则：** 轻量化抽象硬件表达能力，每个 OP 处理一个单元操作。\r\n  - **功能：** 支持硬件特定操作，如 Cube 类算子的快速构建，通过 Microop 封装复杂操作。\r\n  - **优化：** 内存分配、指令映射、流水并行等。\r\n\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw04.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=KPAQKXTgwr2TWJlKfJIhZVd4hgs%3D)\r\n\r\n\r\n#### 4. 辅助方言：\r\n- **Annotation：** 传递属性信息，如内存优化提示。\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw05.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=%2F6cCk6OxM6tnByUFyZV3L4j2FOw%3D)\r\n\r\n- **HACC：** 定义异构硬件相关信息，如函数类型、硬件单元信息。\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw06.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=gzaZ7tYb3TQ958Vy8gfJfJ8zUv4%3D)\r\n\r\n- **Scope：** 代码区域标记，支持代码分块和函数提取。\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw07.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=QXhsGdzEiOuLVhXtGCEcYjDzkSc%3D)\r\n\r\n## HFusion 方言关键 Pass\r\n### 昇腾硬件架构：\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw08.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=E9heCAUeZR%2BD60lKsnGN%2B6K7IOg%3D)\r\n\r\n- AIC核与AIV核分离，各自拥有专属内存和计算单元。\r\n- 核间数据交互通过Global Memory（GM）进行。\r\n\r\n### HFusion 方言 OP 设计\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw09.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=vr4J1tmiJK8KjldOlM1dAFyCRmc%3D)\r\n\r\n### HFusion 预处理层\r\n#### 1. Legalize BF16\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw10.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=EjkaLdANK0hiq7hhgSFbYyDqp4w%3D)\r\n\r\n#### 2. OP Simplification\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw11.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=xa3W7g6SySMCvi3lqhodZasikU0%3D)\r\n\r\n#### 3. Decomposition\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw12.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=J6ru0aW1KwANDpQfGdIM%2Faqp4Ec%3D)\r\n\r\n## HIVM 方言关键 Pass\r\n### HIVM OP 设计原则\r\n- 基础 OP：根据每条芯片指令自底向上轻量化抽象，根据芯片能力校验 OP 约束。\r\n- Macro OP：根据业务场景抽象，由多个处理单元操作复合组成。\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw13.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=HMaAqWhnLJb%2FD9FbjzdhoyJlEiY%3D)\r\n\r\n### HIVM OP 属性设计\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw14.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=hPpZuJ9aFLtIvoMrxKtLXVebqWQ%3D)\r\n\r\n### HIVM OP Interface 设计\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw15.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=EM5kG0CobprO0vrSya3RKLLIdNE%3D)\r\n\r\n### HIVM CV 融合编译优化\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw16.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=weyq7NH8U7BhNhT1w%2BCAy6kq8Lw%3D)\r\n\r\n### HIVM 片上内存映射\r\n#### 1. 片上内存空间推导\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw17.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=TCzHhZkZbFMCLldHRjSDLoEzh8k%3D)\r\n\r\n#### 2. 片上内存格式推导\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw18.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=huUNNztmgrNxymy%2Fth%2BJBxH0%2BOg%3D)\r\n\r\n#### 3. 片上内存自动对齐\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw19.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=ifIq8%2FGMChRpKVLugRkbD%2B%2FxfTA%3D)\r\n\r\n## 调优选项及 Hint\r\n### 毕昇调优编译选项\r\n- 控制多层编译，灵活选择对接层\r\n- 进行功能调试，排查精度\r\n- 细粒度调优性能\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw20.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=ZCyc9v%2BDZXU%2FiqCu%2FIC6P5BB7lE%3D)\r\n\r\n### 细粒度调优 Compiler hint\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw21.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=IIJgGlpnS5gSbkR60bQ87u0BMzs%3D)\r\n\r\n## 总结\r\nAscendNPU IR 作为 MLIR 的开源编译组件，通过多层方言设计和丰富的优化技术，有效支持了多种前端编程语言和昇腾 NPU 的硬件优化。未来将吸引更多开发者和研究者参与，共同推动编译器技术和高性能计算的发展。\r\n\r\n\r\n\r\n![2025冬季训练营课程表](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_kcb.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=KakqsqS%2BgFTMkJAFVsyQX5VKJz4%3D)\r\n\r\n### 💡 学习贴士\r\n更多细节及完整课程内容，请观看直播或查看课程回放。\r\n\r\n链接：https:\u002F\u002Fwww.infinitensor.com\u002Fcamp\u002Fwinter2025\r\n\r\n### 📚 训练营报名持续进行中\r\n扫码报名与加入群聊，或点击 **「阅读原文」** 直达官网报名\r\n\r\n![](https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_ewm.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=RtOMOhXu7GG%2FIVSPi6veXijhgkU%3D)",{"publishTime":7,"createTime":109,"canonicalPath":114,"id":115,"title":116},"\u002Fstudy-material\u002Fstudy-43","study-43","InfiniTensor 冬季训练营 OpenCL 编程第三课《OpenCL 算子的实现与优化》",65,"\u002Fstudy-material\u002Fstudy-44","study-44","markdown",{"publishTime":7,"createTime":109,"canonicalPath":122,"id":123,"title":124},"\u002Fstudy-material\u002Fstudy-45","study-45","InfiniTensor 冬季训练营前沿模型第五课《大模型自主智能体》",{"htmlContent":126,"headings":127},"\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw01.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=scKa%2BKANnxa0JRQqbi7iGpM%2BPzo%3D\" alt=\"\">\u003C\u002Fp>\n\u003Cp>2026 年 1 月 28 日，2025 冬季 InfiniTensor 大模型与人工智能系统训练营 AI 编译器系列第七课《(MLIR)AscendNPU IR 编译堆栈》开讲。\u003C\u002Fp>\n\u003Cp>本节课主要讲解 AscendNPU IR 架构。\u003C\u002Fp>\n\u003Ch2 id=\"ascendnpu-ir-架构概述\">\u003Ca class=\"anchor\" href=\"#ascendnpu-ir-架构概述\" aria-label=\"跳转到标题：AscendNPU IR 架构概述\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>AscendNPU IR 架构概述\u003C\u002Fh2>\u003Ch3 id=\"triton-ascend-ascendnpu-ir\">\u003Ca class=\"anchor\" href=\"#triton-ascend-ascendnpu-ir\" aria-label=\"跳转到标题：Triton-Ascend + AscendNPU IR\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>Triton-Ascend + AscendNPU IR\u003C\u002Fh3>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw02.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=IU0h3kblaeY3ocmOSmY3Y6fseAg%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch3 id=\"mlir-简介\">\u003Ca class=\"anchor\" href=\"#mlir-简介\" aria-label=\"跳转到标题：MLIR 简介：\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>MLIR 简介：\u003C\u002Fh3>\u003Ch4 id=\"1-定义\">\u003Ca class=\"anchor\" href=\"#1-定义\" aria-label=\"跳转到标题：1. 定义：\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>1. 定义：\u003C\u002Fh4>\u003Cul>\n\u003Cli>MLIR（Multi-Level Intermediate Representation）是一种开源的编译基础设施，旨在通过统一且可扩展的中间表示解决软件碎片化和编译效率问题。\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Ch4 id=\"2-特点\">\u003Ca class=\"anchor\" href=\"#2-特点\" aria-label=\"跳转到标题：2. 特点：\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>2. 特点：\u003C\u002Fh4>\u003Cul>\n\u003Cli>多层方言（Dialects）支持，从高层计算图到低层硬件指令的全栈抽象。\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Ch3 id=\"ascendnpu-ir-引入\">\u003Ca class=\"anchor\" href=\"#ascendnpu-ir-引入\" aria-label=\"跳转到标题：AscendNPU IR 引入：\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>AscendNPU IR 引入：\u003C\u002Fh3>\u003Cul>\n\u003Cli>背景：为了支持更多前端编程语言和硬件平台，特别是在NPU（如昇腾NPU）上的优化。\u003C\u002Fli>\n\u003Cli>目标：通过 AscendNPU IR 实现高效编译和硬件优化。\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Ch2 id=\"ascendnpu-ir-架构详解\">\u003Ca class=\"anchor\" href=\"#ascendnpu-ir-架构详解\" aria-label=\"跳转到标题：AscendNPU IR 架构详解\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>AscendNPU IR 架构详解\u003C\u002Fh2>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw03.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=qOhMVKHpuehK4S80l37YCBxhjqY%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch3 id=\"整体架构\">\u003Ca class=\"anchor\" href=\"#整体架构\" aria-label=\"跳转到标题：整体架构：\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>整体架构：\u003C\u002Fh3>\u003Ch4 id=\"1-方言层级\">\u003Ca class=\"anchor\" href=\"#1-方言层级\" aria-label=\"跳转到标题：1. 方言层级：\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>1. 方言层级：\u003C\u002Fh4>\u003Cul>\n\u003Cli>AscendNPU IR 采用多层方言设计，主要包括 Hfusion 和 HIVM 两层核心方言，辅以Annotation、HACC、Scope等辅助方言。\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Ch4 id=\"2-转换流程\">\u003Ca class=\"anchor\" href=\"#2-转换流程\" aria-label=\"跳转到标题：2. 转换流程：\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>2. 转换流程：\u003C\u002Fh4>\u003Cul>\n\u003Cli>从前端 DSL 到 Triton IR，再到 TritonGPU IR（或 MLIR 公共方言如 Linalg），最终转换为AscendNPU IR，并编译成二进制文件。\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Ch4 id=\"3-核心方言解析\">\u003Ca class=\"anchor\" href=\"#3-核心方言解析\" aria-label=\"跳转到标题：3. 核心方言解析：\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>3. 核心方言解析：\u003C\u002Fh4>\u003Cul>\n\u003Cli>\u003Cstrong>Hfusion：\u003C\u002Fstrong>\u003Cul>\n\u003Cli>\u003Cstrong>设计原理：\u003C\u002Fstrong> 基于 Linalg 的扩展，采用命名 OP 保留高层语义信息。\u003C\u002Fli>\n\u003Cli>\u003Cstrong>功能：\u003C\u002Fstrong> 数据预处理、OP 简化、类型转换等，不直接涉及硬件细节。\u003C\u002Fli>\n\u003Cli>\u003Cstrong>优化：\u003C\u002Fstrong> 合法性检查、冗余操作消除、高层 OP 分解等。\u003C\u002Fli>\n\u003C\u002Ful>\n\u003C\u002Fli>\n\u003Cli>\u003Cstrong>HIVM：\u003C\u002Fstrong>\u003Cul>\n\u003Cli>\u003Cstrong>设计原则：\u003C\u002Fstrong> 轻量化抽象硬件表达能力，每个 OP 处理一个单元操作。\u003C\u002Fli>\n\u003Cli>\u003Cstrong>功能：\u003C\u002Fstrong> 支持硬件特定操作，如 Cube 类算子的快速构建，通过 Microop 封装复杂操作。\u003C\u002Fli>\n\u003Cli>\u003Cstrong>优化：\u003C\u002Fstrong> 内存分配、指令映射、流水并行等。\u003C\u002Fli>\n\u003C\u002Ful>\n\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw04.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=KPAQKXTgwr2TWJlKfJIhZVd4hgs%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch4 id=\"4-辅助方言\">\u003Ca class=\"anchor\" href=\"#4-辅助方言\" aria-label=\"跳转到标题：4. 辅助方言：\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>4. 辅助方言：\u003C\u002Fh4>\u003Cul>\n\u003Cli>\u003Cstrong>Annotation：\u003C\u002Fstrong> 传递属性信息，如内存优化提示。\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw05.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=%2F6cCk6OxM6tnByUFyZV3L4j2FOw%3D\" alt=\"\">\u003C\u002Fp>\n\u003Cul>\n\u003Cli>\u003Cstrong>HACC：\u003C\u002Fstrong> 定义异构硬件相关信息，如函数类型、硬件单元信息。\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw06.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=gzaZ7tYb3TQ958Vy8gfJfJ8zUv4%3D\" alt=\"\">\u003C\u002Fp>\n\u003Cul>\n\u003Cli>\u003Cstrong>Scope：\u003C\u002Fstrong> 代码区域标记，支持代码分块和函数提取。\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw07.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=QXhsGdzEiOuLVhXtGCEcYjDzkSc%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch2 id=\"hfusion-方言关键-pass\">\u003Ca class=\"anchor\" href=\"#hfusion-方言关键-pass\" aria-label=\"跳转到标题：HFusion 方言关键 Pass\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>HFusion 方言关键 Pass\u003C\u002Fh2>\u003Ch3 id=\"昇腾硬件架构\">\u003Ca class=\"anchor\" href=\"#昇腾硬件架构\" aria-label=\"跳转到标题：昇腾硬件架构：\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>昇腾硬件架构：\u003C\u002Fh3>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw08.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=E9heCAUeZR%2BD60lKsnGN%2B6K7IOg%3D\" alt=\"\">\u003C\u002Fp>\n\u003Cul>\n\u003Cli>AIC核与AIV核分离，各自拥有专属内存和计算单元。\u003C\u002Fli>\n\u003Cli>核间数据交互通过Global Memory（GM）进行。\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Ch3 id=\"hfusion-方言-op-设计\">\u003Ca class=\"anchor\" href=\"#hfusion-方言-op-设计\" aria-label=\"跳转到标题：HFusion 方言 OP 设计\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>HFusion 方言 OP 设计\u003C\u002Fh3>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw09.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=vr4J1tmiJK8KjldOlM1dAFyCRmc%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch3 id=\"hfusion-预处理层\">\u003Ca class=\"anchor\" href=\"#hfusion-预处理层\" aria-label=\"跳转到标题：HFusion 预处理层\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>HFusion 预处理层\u003C\u002Fh3>\u003Ch4 id=\"1-legalize-bf16\">\u003Ca class=\"anchor\" href=\"#1-legalize-bf16\" aria-label=\"跳转到标题：1. Legalize BF16\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>1. Legalize BF16\u003C\u002Fh4>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw10.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=EjkaLdANK0hiq7hhgSFbYyDqp4w%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch4 id=\"2-op-simplification\">\u003Ca class=\"anchor\" href=\"#2-op-simplification\" aria-label=\"跳转到标题：2. OP Simplification\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>2. OP Simplification\u003C\u002Fh4>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw11.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=xa3W7g6SySMCvi3lqhodZasikU0%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch4 id=\"3-decomposition\">\u003Ca class=\"anchor\" href=\"#3-decomposition\" aria-label=\"跳转到标题：3. Decomposition\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>3. Decomposition\u003C\u002Fh4>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw12.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=J6ru0aW1KwANDpQfGdIM%2Faqp4Ec%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch2 id=\"hivm-方言关键-pass\">\u003Ca class=\"anchor\" href=\"#hivm-方言关键-pass\" aria-label=\"跳转到标题：HIVM 方言关键 Pass\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>HIVM 方言关键 Pass\u003C\u002Fh2>\u003Ch3 id=\"hivm-op-设计原则\">\u003Ca class=\"anchor\" href=\"#hivm-op-设计原则\" aria-label=\"跳转到标题：HIVM OP 设计原则\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>HIVM OP 设计原则\u003C\u002Fh3>\u003Cul>\n\u003Cli>基础 OP：根据每条芯片指令自底向上轻量化抽象，根据芯片能力校验 OP 约束。\u003C\u002Fli>\n\u003Cli>Macro OP：根据业务场景抽象，由多个处理单元操作复合组成。\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw13.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=HMaAqWhnLJb%2FD9FbjzdhoyJlEiY%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch3 id=\"hivm-op-属性设计\">\u003Ca class=\"anchor\" href=\"#hivm-op-属性设计\" aria-label=\"跳转到标题：HIVM OP 属性设计\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>HIVM OP 属性设计\u003C\u002Fh3>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw14.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=hPpZuJ9aFLtIvoMrxKtLXVebqWQ%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch3 id=\"hivm-op-interface-设计\">\u003Ca class=\"anchor\" href=\"#hivm-op-interface-设计\" aria-label=\"跳转到标题：HIVM OP Interface 设计\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>HIVM OP Interface 设计\u003C\u002Fh3>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw15.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=EM5kG0CobprO0vrSya3RKLLIdNE%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch3 id=\"hivm-cv-融合编译优化\">\u003Ca class=\"anchor\" href=\"#hivm-cv-融合编译优化\" aria-label=\"跳转到标题：HIVM CV 融合编译优化\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>HIVM CV 融合编译优化\u003C\u002Fh3>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw16.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=weyq7NH8U7BhNhT1w%2BCAy6kq8Lw%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch3 id=\"hivm-片上内存映射\">\u003Ca class=\"anchor\" href=\"#hivm-片上内存映射\" aria-label=\"跳转到标题：HIVM 片上内存映射\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>HIVM 片上内存映射\u003C\u002Fh3>\u003Ch4 id=\"1-片上内存空间推导\">\u003Ca class=\"anchor\" href=\"#1-片上内存空间推导\" aria-label=\"跳转到标题：1. 片上内存空间推导\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>1. 片上内存空间推导\u003C\u002Fh4>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw17.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=TCzHhZkZbFMCLldHRjSDLoEzh8k%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch4 id=\"2-片上内存格式推导\">\u003Ca class=\"anchor\" href=\"#2-片上内存格式推导\" aria-label=\"跳转到标题：2. 片上内存格式推导\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>2. 片上内存格式推导\u003C\u002Fh4>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw18.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=huUNNztmgrNxymy%2Fth%2BJBxH0%2BOg%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch4 id=\"3-片上内存自动对齐\">\u003Ca class=\"anchor\" href=\"#3-片上内存自动对齐\" aria-label=\"跳转到标题：3. 片上内存自动对齐\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>3. 片上内存自动对齐\u003C\u002Fh4>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw19.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=ifIq8%2FGMChRpKVLugRkbD%2B%2FxfTA%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch2 id=\"调优选项及-hint\">\u003Ca class=\"anchor\" href=\"#调优选项及-hint\" aria-label=\"跳转到标题：调优选项及 Hint\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>调优选项及 Hint\u003C\u002Fh2>\u003Ch3 id=\"毕昇调优编译选项\">\u003Ca class=\"anchor\" href=\"#毕昇调优编译选项\" aria-label=\"跳转到标题：毕昇调优编译选项\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>毕昇调优编译选项\u003C\u002Fh3>\u003Cul>\n\u003Cli>控制多层编译，灵活选择对接层\u003C\u002Fli>\n\u003Cli>进行功能调试，排查精度\u003C\u002Fli>\n\u003Cli>细粒度调优性能\u003Cbr>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw20.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=ZCyc9v%2BDZXU%2FiqCu%2FIC6P5BB7lE%3D\" alt=\"\">\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Ch3 id=\"细粒度调优-compiler-hint\">\u003Ca class=\"anchor\" href=\"#细粒度调优-compiler-hint\" aria-label=\"跳转到标题：细粒度调优 Compiler hint\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>细粒度调优 Compiler hint\u003C\u002Fh3>\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_44_zw21.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=IIJgGlpnS5gSbkR60bQ87u0BMzs%3D\" alt=\"\">\u003C\u002Fp>\n\u003Ch2 id=\"总结\">\u003Ca class=\"anchor\" href=\"#总结\" aria-label=\"跳转到标题：总结\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>总结\u003C\u002Fh2>\u003Cp>AscendNPU IR 作为 MLIR 的开源编译组件，通过多层方言设计和丰富的优化技术，有效支持了多种前端编程语言和昇腾 NPU 的硬件优化。未来将吸引更多开发者和研究者参与，共同推动编译器技术和高性能计算的发展。\u003C\u002Fp>\n\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_kcb.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=KakqsqS%2BgFTMkJAFVsyQX5VKJz4%3D\" alt=\"2025冬季训练营课程表\">\u003C\u002Fp>\n\u003Ch3 id=\"学习贴士\">\u003Ca class=\"anchor\" href=\"#学习贴士\" aria-label=\"跳转到标题：💡 学习贴士\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>💡 学习贴士\u003C\u002Fh3>\u003Cp>更多细节及完整课程内容，请观看直播或查看课程回放。\u003C\u002Fp>\n\u003Cp>链接：\u003Ca href=\"https:\u002F\u002Fwww.infinitensor.com\u002Fcamp\u002Fwinter2025\">https:\u002F\u002Fwww.infinitensor.com\u002Fcamp\u002Fwinter2025\u003C\u002Fa>\u003C\u002Fp>\n\u003Ch3 id=\"训练营报名持续进行中\">\u003Ca class=\"anchor\" href=\"#训练营报名持续进行中\" aria-label=\"跳转到标题：📚 训练营报名持续进行中\">\u003Cspan class=\"octicon octicon-link\">\u003C\u002Fspan>\u003C\u002Fa>📚 训练营报名持续进行中\u003C\u002Fh3>\u003Cp>扫码报名与加入群聊，或点击 \u003Cstrong>「阅读原文」\u003C\u002Fstrong> 直达官网报名\u003C\u002Fp>\n\u003Cp>\u003Cimg src=\"https:\u002F\u002Foss.infinitensor.com\u002Fprod\u002Fimages\u002FKnowledge_Base\u002FKB_ewm.jpg?Expires=1792752562&OSSAccessKeyId=LTAI5t9R6uzvTa69CT92cFvV&Signature=RtOMOhXu7GG%2FIVSPi6veXijhgkU%3D\" alt=\"\">\u003C\u002Fp>\n",[128,131,134,137,141,144,147,150,153,156,159,162,165,168,171,174,177,180,183,186,189,192,195,198,201,204,207,210,213,216,218,221,223,226],{"id":129,"text":130,"level":110},"ascendnpu-ir-架构概述","AscendNPU IR 架构概述",{"id":132,"text":133,"level":9},"triton-ascend-ascendnpu-ir","Triton-Ascend + AscendNPU IR",{"id":135,"text":136,"level":9},"mlir-简介","MLIR 简介：",{"id":138,"text":139,"level":140},"1-定义","1. 定义：",4,{"id":142,"text":143,"level":140},"2-特点","2. 特点：",{"id":145,"text":146,"level":9},"ascendnpu-ir-引入","AscendNPU IR 引入：",{"id":148,"text":149,"level":110},"ascendnpu-ir-架构详解","AscendNPU IR 架构详解",{"id":151,"text":152,"level":9},"整体架构","整体架构：",{"id":154,"text":155,"level":140},"1-方言层级","1. 方言层级：",{"id":157,"text":158,"level":140},"2-转换流程","2. 转换流程：",{"id":160,"text":161,"level":140},"3-核心方言解析","3. 核心方言解析：",{"id":163,"text":164,"level":140},"4-辅助方言","4. 辅助方言：",{"id":166,"text":167,"level":110},"hfusion-方言关键-pass","HFusion 方言关键 Pass",{"id":169,"text":170,"level":9},"昇腾硬件架构","昇腾硬件架构：",{"id":172,"text":173,"level":9},"hfusion-方言-op-设计","HFusion 方言 OP 设计",{"id":175,"text":176,"level":9},"hfusion-预处理层","HFusion 预处理层",{"id":178,"text":179,"level":140},"1-legalize-bf16","1. Legalize BF16",{"id":181,"text":182,"level":140},"2-op-simplification","2. OP Simplification",{"id":184,"text":185,"level":140},"3-decomposition","3. Decomposition",{"id":187,"text":188,"level":110},"hivm-方言关键-pass","HIVM 方言关键 Pass",{"id":190,"text":191,"level":9},"hivm-op-设计原则","HIVM OP 设计原则",{"id":193,"text":194,"level":9},"hivm-op-属性设计","HIVM OP 属性设计",{"id":196,"text":197,"level":9},"hivm-op-interface-设计","HIVM OP Interface 设计",{"id":199,"text":200,"level":9},"hivm-cv-融合编译优化","HIVM CV 融合编译优化",{"id":202,"text":203,"level":9},"hivm-片上内存映射","HIVM 片上内存映射",{"id":205,"text":206,"level":140},"1-片上内存空间推导","1. 片上内存空间推导",{"id":208,"text":209,"level":140},"2-片上内存格式推导","2. 片上内存格式推导",{"id":211,"text":212,"level":140},"3-片上内存自动对齐","3. 片上内存自动对齐",{"id":214,"text":215,"level":110},"调优选项及-hint","调优选项及 Hint",{"id":217,"text":217,"level":9},"毕昇调优编译选项",{"id":219,"text":220,"level":9},"细粒度调优-compiler-hint","细粒度调优 Compiler hint",{"id":222,"text":222,"level":110},"总结",{"id":224,"text":225,"level":9},"学习贴士","💡 学习贴士",{"id":227,"text":228,"level":9},"训练营报名持续进行中","📚 训练营报名持续进行中"]